The invention relates to data communication systems. More particularly the invention relates to systems for the communication of serial data.
As the application of electronic control systems becomes more widespread and complex, the need for data to be sent about such systems with high reliability has become an important factor. To minimize the complexity and cost of communication links, multiplexed or serial communication systems are used. However, it is necessary that the circuitry communicating upon a serial link be as simple and hence as cost-effective as possible while being very reliable. Coding systems currently used are generally either not reliable enough or far too complicated and would take up a lot of space within a device. An example of the latter case is that of cyclic redundancy coding (CRC) where large check words are generated and sent along with the data word. The generation of such a coding sequence requires extensive shift register networks to implement coding polynomials and with increasing use of ASIC technology such large coding systems are expensive.
European Patent Specification EP0013103 describes a system that splits up a message into two components, an address part and a data part. For error checking, these two components may be seen as two separate blocks, each block having its own error check. The block is received by clocking it into a shift register. It is then transferred to an intermediate register. The inverse of the block is then received in the original shift register. Each bit is compared with its inverse after receipt, i.e., the word in the shift register is compared with the word in the intermediate register for the inverse relationship.
United Kingdom Patent Specification GB1374228 discloses the use of a long shift register in which is stored both the true message and its inverse. Only after the full message has been received are the stages of the shift register containing corresponding bits of the true and inverse parts of the message compared. An error signal is provided if the correct relationship does not exist for all the comparisons.
Further, another United Kingdom Patent Specification GB2144606B describes sending data as pairs of bits, a true bit and a complement bit. This is used to remove any dc component from the resulting signal. The method of error detection requires receiving a complete message and then performing the error check.
An object of the invention is to provide a system for serial data transmission which is reliable and uncomplicated.
According to one aspect of the invention there is provided a method of verifying the accurate transmission of an n-bit word comprising transmitting the n-bit word followed by transmitting an inversion of the n-bit word, receiving the words in an n-bit shift register and checking for inversion of the n+ bit and all subsequent bits up to n+n bits by synchronized comparison with the corresponding output of the shift register, and providing an accept signal only if all the compared bits are inversions of one another; the word then stored in the shift register being the accurate inversion of the n-bit word.
The method may comprise sending the n-bit word again after transmitting the inverted n-bit word in which case the checking for inversion is carried out for n+1 to n+2n bits, in which case the word then stored in the shift register is the n-bit word and not its inversion; the checking having been carried out twice.
In a similar manner the transmitting method may include transmitting the n-bit word several times an alternatively sending the inversion of the word so that the checking is carried out three or more times respectively.
According to another aspect of the invention there is provided an apparatus for checking the accuracy of serially transmitted data, the apparatus including a transmitter for sending the n-bit words of data and an inversion of the n-bit words alternatively, an n-bit shift register for receiving the data, means for comparing the first stage of the register with its output arranged to provide a accept signal if that stage and the output are inversions of one another for all the data received after the first nth bit.